In recent years, one of the more poplar topics panel discussions at computer conferences and trade { A } has been the"RISC versus CISC"debate.

　　RISC processors feature a small number of instructions that each executes in { B } machine cycle. CISC processors use complex instructions that can take several cycles to execute.

　　The RISC Versus CISC debate won't be decided by panel discussion 1 it will be won in the marketplace. And the deciding factor may have little to do with { C } of instructions and registers) and more to do with parallelism.

　　Since their conception, RISC processors have been evolving toward microparallelism, in corporating parallel-processing features { D } the processor. RISC processors feature pipelining, whereby many instructions can be decoded while one instruction executes.

　　RISC processor, however, are moving to toward pipelines for each unit of the processor.

　　CISC processors also employ pipelining. They have many interger instructions that execute in one cycle, but the varying execution times of CISC instructions { E } the effectiveness of parallelis.

　　供選擇的答案

　　A～E：①union ②two ③numbers ④between ⑤limit

　　⑥contents ⑦shows ⑧one ⑨within ⑩enhance

　　【解析】

　　參考譯文：近年來，在計算機學術會議和貿易展覽會上***的會場討論課題之一是"RISC對CISC"的爭論。

　　RISC處理器以少量指令為特征，且每條指令在一個機器周期中執行。CISC處理器使用復雜的指令，它們可能花費若干周期來執行。

　　RISC對CISC的爭議將不由會場討論來作結論，它將在市場中定勝負。并且，決定的因素也許很少取決于指令和寄存器的數目，而更多取決于并行性。

　　自從RISC概念提出后，RISC處理器正向著微并行性發展，它在處理器內部結合了并行處理的特性。RISC處理器以流水線為特點，在流水線上當一條指令執行時，許多指令能被解碼。況且，RISC處理器正向著每個處理器單元多流水線發展。

　　CISC處理器也使用流水線。它們有許多在一個周期中執行的整數指令，但是CISC指令變化的執行時間限制了并行性的效率。

　　【答案】A：⑦ B：⑧ C：③ D：⑨ E：⑤